12 个稳定版本

新版本 1.1.2 2024 年 8 月 20 日
1.1.1 2024 年 4 月 8 日
1.1.0 2023 年 12 月 17 日
1.0.0 2023 年 11 月 29 日

#23模拟

Download history 1/week @ 2024-05-16 3/week @ 2024-06-27 41/week @ 2024-07-04 132/week @ 2024-08-15

132 每月下载量

MIT 许可证

540KB
13K SLoC

GSim 是一个针对高速模拟优化的数字电路模拟引擎。

使用示例

use gsim::*;
use std::num::NonZeroU8;

pub fn main() {
    let mut builder = SimulatorBuilder::default();

    // Add wires and components to the simulation
    let wire_width = NonZeroU8::new(1).unwrap();
    let input_a = builder.add_wire(wire_width).unwrap();
    let input_b = builder.add_wire(wire_width).unwrap();
    let output = builder.add_wire(wire_width).unwrap();
    // The gate ID is not usefull to us because we don't intend on reading its data
    let _gate = builder.add_and_gate(&[input_a, input_b], output).unwrap();

    // Create the simulation
    let mut sim = builder.build();

    // Manually drive the input wires
    sim.set_wire_drive(input_a, &LogicState::from_bool(true)).unwrap();
    sim.set_wire_drive(input_b, &LogicState::from_bool(false)).unwrap();

    // Run the simulation
    const MAX_STEPS: u64 = 2;
    match sim.run_sim(MAX_STEPS) {
        SimulationRunResult::Ok => {}
        SimulationRunResult::MaxStepsReached => panic!("simulation did not settle within allowed steps"),
        SimulationRunResult::Err(err) => panic!("simulation error: {err:?}"),
    }

    // Make sure we got the expected result
    let output_state = sim.get_wire_state(output).unwrap();
    assert!(output_state.eq(&LogicState::from_bool(false), wire_width));
}

依赖项

~2.5–9MB
~80K SLoC